IBIS Macromodel Task Group Meeting date: 04 May 2010 Members (asterisk for those attending): Adge Hawes, IBM Y* Ambrish Varma, Cadence Design Systems Y* Anders Ekholm, Ericsson * Arpad Muranyi, Mentor Graphics Corp. Barry Katz, SiSoft Y* Bob Ross, Teraspeed Consulting Group Brad Brim, Sigrity Brad Griffin, Cadence Design Systems Chris Herrick, Ansoft Chris McGrath, Synopsys Y* Danil Kirsanov, Ansoft David Banas, Xilinx Deepak Ramaswany, Ansoft Donald Telian, consultant Doug White, Cisco Systems Y* Eckhard Lenski, Nokia-Siemens Networks Eckhard Miersch, Sigrity Essaid Bensoudane, ST Microelectronics Y* Fangyi Rao, Agilent Ganesh Narayanaswamy, ST Micro Gang Kang, Sigrity Hemant Shah, Cadence Design Systems Ian Dodd, consultant Jerry Chuang, Xilinx Joe Abler, IBM Y* John Angulo, Mentor Graphics John Shields, Mentor Graphics Y* Ken Willis, Sigrity Kellee Crisafulli, Celsionix Kumar Keshavan, Sigrity Lance Wang, Cadence Design Systems Luis Boluna, Cisco Systems Michael Mirmak, Intel Corp. Y* Mike LaBonte, Cisco Systems Mike Steinberger, SiSoft Mustansir Fanaswalla, Xilinx Patrick O'Halloran, Tiburon Design Automation Paul Fernando, NCSU Pavani Jella, TI Radek Biernacki, Agilent (EESof) Y* Randy Wolff, Micron Technology Ray Komow, Cadence Design Systems Richard Mellitz, Intel Richard Ward, Texas Instruments Samuel Mertens, Ansoft Sam Chitwood, Sigrity Sanjeev Gupta, Agilent * Scott McMorrow, Teraspeed Consulting Group Shangli Wu, Cadence Design Systems Sid Singh, Extreme Networks Stephen Scearce, Cisco Systems Steve Kaufer, Mentor Graphics Steve Pytel, Ansoft Syed Huq, Cisco Systems Syed Sadeghi, ST Micro Ted Mido, Synopsys Terry Jernberg, Cadence Design Systems * Todd Westerhoff, SiSoft Vladimir Dmitriev-Zdorov, Mentor Graphics Vikas Gupta, Xilinx Vuk Borich, Agilent Y* Walter Katz, SiSoft Wenyi Jin, LSI Logic Zhen Mu, Mentor Graphics ------------------------------------------------------------------------ Opens: - Mike asked if there would be a meeting next week - The European summit is Wednesday - Not able to attend: Bob, Danil, Eckhard, Anders - There will be a meeting next week -------------------------- Call for patent disclosure: - No one declared a patent. ------------- Review of ARs: - Scott to rewrite clock times BIRD - Arpad has not heard from Scott - We will not vote on it today - Arpad update truth table based on discussion from last week - Done, will cover today - Arpad: Write parameter passing syntax proposal (BIRD draft) for *-AMS models in IBIS that is consistent with the parameter passing syntax of the AMI models - TBD - TBD: Propose a parameter passing syntax for the SPICE - [External ...] also? - TBD - Arpad: Review the documentation (annotation) in the macro libraries. - Deferred until a demand arises or we have nothing else to do ------------- New Discussion: Arpad showed the clock_times BIRD: - Scott: There was feedback about language consistency with the IBIS spec - No other changes were made - Arpad: What should the EDA tool do when clocks are missing? - There may be an interruption in the clock returns - Scott: The tool has two choices: 1) A receiver might never produce clocks - The tool should interpret the eye pattern to recover the clock 2) Treat it like the trigger point on an oscilloscope - Statistically this is the right way - Arpad: Is there a problem discarding clock ticks? - Scott: Having no clock tick may mean the bit is ignored by the receiver: - A bit error check would tell if something is wrong - Walter: Since this is GetWave we are not doing statistical analysis - Scott: It is still valid to analyze time domain data statistically - To extrapolate BER profiles for example - Walter: Always thought it would emulate a real TDR - Arpad: Vladimir sent email: "Walter said that every EDA platform should give the same results" - Walter: Only the DLL output must be the same: - An error every 10e6 is a disaster - Any missing ticks are a problem - Parallel clock recovery is still valuable though - Scott: It would work like a compliance measurement - These are designed to force aberrant behavior - We might want to force CDR out of lock - Arpad: Should we write something in the BIRD about this? - Scott: That should be left to EDA vendors - Walter: Models that miss clock ticks should have comments - Arpad: Are we ready to vote on submitting this? - Mike: It is Scott's BIRD, do we need to vote? - Arpad: We should be clear about if we all agree with this - Scott: It may help for people to know that the group approves Arpad called for a vote on whether this group approves of the clock_times BIRD proposed by Scott McMorrow: - Votes: Cadence Design Systems Yes Ericsson Yes Teraspeed Consulting Group Yes Ansoft Yes Nokia-Siemens Networks Yes Agilent Yes Mentor Graphics Yes Sigrity Yes Cisco Systems Yes Micron Technology Yes SiSoft Yes - The group approved unanimously Arpad showed the truth table spreadsheet: - Row 14: - Arpad: Should we require min <= default <= max? - Todd: Why should we let default be an illegal value? - We accepted the rule - Rows 16 & 17: - Arpad: Blue comments come from emails - They constitute a disagreement - Walter: There are two different things here: - Default must be in legal format - If Format is specified Default must be an allowed value - If no Default, Value is not needed, and vice-versa - Files written to 5.0 will satisfy this rule - Arpad: Why do we need a Default where nothing is passed to the DLL? Arpad showed the AMI flow document: - Arpad: Truth table on slide 3 - This differs from Ambrish - Do we agree on this? - Todd: This is correct, but: - Because Init_Returns_Impulse is placed in memory, the tool doesn't have to make flow decisions - This is not good coding practice though - Ambrish: Agree - Statistical and time domain are separate flows - We should have separate tables for these - Fangyi: The T/F in the outside boxes are not needed - Todd: Separate statistical and time domain tables would be easier to understand - Arpad: A single page can be seen all at once - Fangyi: Init calls are sequential in time domain - So not all combinations would be needed - Todd: This will get complicated when we have GetWave digital input - We should generate both tables to see if they are redundant - Ambrish: Can we have truth tables that are not in a box? - Arpad: We have to spell out the steps between function calls - Fangyi: The flow is more important than the truth table - The one Ambrish sent was like that - Arpad: The T/F in the TX Init box is because it outputs different things - Mike: In flow diagrams the lines are usually labeled to show that - Arpad: TX Init and Rx_Init might both output different equations - Fangyi: That is the choice of the model, not the simulator - Arpad: So we should say nothing about what is convolved? - Fangyi: Right - Ambrish: Right - Todd: The flow in current spec is correct for analog input to TX GetWave - Fangyi: Right - Ambrish: Right - Arpad: Then we need no changes? - Todd: We need to clarify statistical - TX GetWave is not functional in the current spec for analog Next meeting: 11 May 2010 12:00pm PT -------- IBIS Interconnect SPICE Wish List: 1) Simulator directives